A programmable logic device (PLD) is designed to be user-programmable so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream, typically from off-chip memory, into configuration memory cells of the FPGA.
For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLDs and systems including PLDs also have different “modes” depending on the operations being performed on them. A specific protocol allows a PLD to enter into the appropriate mode. Typical PLDs have internal blocks of configuration memory which specify how each of the programmable cells will emulate the user's logic. During a “program” mode, a configuration bitstream is provided to non-volatile memory, such as a read-only memory (ROM) (e.g., a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM)) either external or internal to the programmable logic device. Each address is typically accessed by specifying its row and column addresses. During system power up of a “startup” mode, the configuration bits are successively loaded from the non-volatile memory into static random access memory (SRAM) configuration latches of a configuration logic block. At the end of the start-up, the PLD is now specialized to the user's design, and the PLD enters into “user” mode as part of its normal operation.
Function generators comprising look-up table random access memories (LUT RAMs) are currently employed as building blocks for configurable logic blocks, and provide pipelining structures such as LUT RAM-based shift registers. The function generators can be selected to have different functions which are selected by configuration data bits downloaded in a configuration bitstream and loaded into configuration memory. For example, a function generator may be implemented as a LUT RAM (also commonly called distributed RAM) or a shift register. An example of a look-up table is a 16:1 multiplexer with the four inputs serving as binary select lines, and the sixteen values programmed into the look-up table serving as the data being selected. When implemented as a shift register, each input to the multiplexer is coupled to an associated flip-flop that makes up the overall logic cell. The addressable bit of the shift register may be stored in the flip-flop for a synchronous output, or may be fed directly to a combinatorial output of a CLB. A RAM-based shift register module provides a very efficient multi-bit wide shift register for use in FIFO-like applications or as a delay line or time skew buffer. Fixed-length shift registers and variable-length shift registers may be created. Accordingly, using LUT RAM-based shift registers may improve performance and rapidly lead to cost savings in circuits requiring shift registers.
However, all such LUT structures of conventional programmable logic devices may be reset globally only at initial configuration. Thus, a reset option is not available during or subsequent to a partial reconfiguration cycle of a programmable logic circuit, resulting in instantiated configurations nominally initialized to unknown state. While a partial reconfiguration of a PLD may be achieved in a conventional device by changing the configuration bits to change the configuration of one or more CLBs, the states of the memory cells of the LUT structures are not changed. That is, it is possible in conventional devices to change the states of configuration memory cells that determine the configuration of a CLB, but it is not possible to change the state of the memory cells of the LUT structures which are left with irrelevant data. Therefore, the state of LUT structures is essentially unmanageable in any partially reconfigurable design employing these structures, resulting in an un-mappable logic resource. Within the context of Self-Reconfiguring Platform (SRP) processing, a correct state must be maintained across all partial reconfiguration cycles. In SRAM-based FPGAs, configuration resources may be reused as stateful structures, (i.e., logic-level resources possessing state), as typified by LUT-RAMs, shift registers, etc. Such structures may prove highly efficient/compact within context of design synthesis and mapping. However, these structures do not possess logically-exposed reset inputs (i.e., a reset for which there exists an explicit datapath representation). Therefore, conventional programmable logic circuits may not be initialized to a known state subsequent to a partial reconfiguration cycle. This leads to practical difficulties for use of these structures within the context of an SRP design implementation.
Accordingly, there is a need for an improved circuit for and method of enabling partial reconfiguration of memory cells of a programmable logic device.